1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer interconnection structure.
2. Description of Related Art
A so-called multilayer interconnection structure, in which a plurality of wiring layers are laminated on a semiconductor substrate, is widely employed in semiconductor devices. In semiconductor devices having such a multilayer interconnection structure, in place of Al (aluminum) which has been conventionally used, use of Cu (copper) which has a higher conductivity, as a wiring material for reducing wiring resistance is being examined.
FIGS. 3A to 3D are schematic sectional views showing, in order of process, a method for manufacturing upper layer wirings in a multilayer interconnection structure using Cu as a wiring material.
In a semiconductor device having a multilayer interconnection structure, first, on a semiconductor substrate 102 made of Si (silicon), a first interlayer insulating film 103 made of SiOC (silicon oxide with carbon added), a middle etching stopper film 104 made of SiCO (silicon carbide with oxygen added), and a first wiring layer 105 made of SiOC are laminated in that order from the semiconductor substrate 102 side as shown in FIG. 3A.
In the first wiring layer 105 and the middle etching stopper film 104, a first lower groove 106 and a second lower groove 107 are formed spaced apart from each other. In the first lower groove 106, a first lower layer wiring 109 made of Cu is embedded via a barrier film 108 made of Ta (tantalum). In the second lower groove 107, a second lower layer wiring 111 made of Cu is embedded via a barrier film 110 made of Ta.
A contact hole 112 is formed in the first interlayer insulating film 103. The contact hole 112 is formed in the first interlayer insulating film 103 by digging in from a bottom surface of the first lower groove 106 and reaches the semiconductor substrate 102. A contact plug 114 made of Cu is embedded in the contact hole 112 via a barrier film 113 made of Ta. The first lower layer wiring 109 is thereby electrically connected to the semiconductor substrate 102 via the contact plug 114.
In an upper layer wiring forming step, first, as shown in FIG. 3A, an etching stopper film 115 having a laminated structure of an SiCO layer and an SiCN (silicon carbonitride) layer, a second interlayer insulating film 116 made of SiOC, a middle etching stopper film 117 made of SiCO and a second wiring layer 118 made of SiCO are laminated in that order from the semiconductor substrate 102 side on the first wiring layer 105, the first lower layer wiring 109 and the second lower layer wiring 111. Thereafter, by etching of the second wiring layer 118, the middle etching stopper film 117 and the second interlayer insulating film 116, a via hole 119 reaching the etching stopper film 115 from an upper surface of the second wiring layer 118 is formed. A bulk 120 is embedded inside the via hole 119. Thereafter, a resist film 121 having openings respectively at a portion including the via hole 119 in a plan view and a portion spaced apart from the aforementioned portion is formed on the second wiring layer 118.
Then, as shown in FIG. 3B, by etching using the resist film 121 as a mask, a first upper groove 122 and a second upper groove 123 are formed in the second wiring layer 118.
Thereafter, as shown in FIG. 3C, the resist film 121 and the bulk 120 are removed by ashing.
Next, as shown in FIG. 3D, a portion of the etching stopper film 115 facing the via hole 119 is removed by etching. An opening 124 in communication with the via hole 119 and partially exposing an upper surface of the first lower layer wiring 109 is thereby penetratingly formed in the etching stopper film 115.
Thereafter, a barrier film (not shown) made of a material having a barrier property with respect to diffusion of Cu is coated onto inner surfaces of the first upper groove 122, the second upper groove 123 and the via hole 119 (including the opening 124). Then, by completely filling the inner side of the barrier film with Cu, a first upper layer wiring, a second upper layer wiring and a via (none of which are shown) are formed in the first upper groove 122, the second upper groove 123 and the via hole 119.
The middle etching stopper film 117 is made of the same material as the etching stopper film 115, in other words, of SiCO. Thus, in the process of forming the opening 124 in the etching stopper film 115, the middle etching stopper film 117 is etched along with the etching stopper film 115. When the middle etching stopper film 117 is removed by etching and the second interlayer insulating film 116 below it is exposed, the second interlayer insulating film 116 becomes etched. Consequently, because the second interlayer insulating film 116 becomes small in thickness, a parasitic capacitance arising across the second lower layer wiring 111 and the second upper layer wiring becomes large.
Further, etching of the second interlayer insulating film 116 may progress extremely at peripheral edge portions of bottom surfaces of the first upper groove 122 and the second upper groove 123, and undesired recesses 125 may form at these portions. In this case, by the first upper layer wiring and the second upper layer wiring entering into the recesses 125, an interval between the portion of the second upper layer wiring entering into the recess 125 and the second lower wiring 111 may become especially small, and this causes lowering of withstand voltage and increase of leak current therebetween. Further, by the first upper layer wiring and the second upper layer wiring entering into the recesses 125, cross sectional areas of the first upper layer wiring and the second upper layer wiring become non-uniform. Consequently, wiring resistances of the first upper layer wiring and the second upper layer wiring become non-uniform.